ACADEMIC BACKGROUND

1. Name Surname

 : Uğur ÇİNİ

2. Date of Birth

 :

3. Title

 : Dr. Öğr. Üyesi

Contact Information

: ugur.cini@uskudar.edu.tr

4. Educational Background

Degree Department University Year
BSc Elektronik ve Haberleşme Müh. Yıldız Teknik Üniversitesi 1999
MSc Elektrik-Elektronik Müh. Boğaziçi Üniversitesi 2003
PhD Elektrik-Elektronik Müh. Boğaziçi Üniversitesi 2010

5. Academic Titles

Degree Department University Year

6. Supervised Theses

6.1. Master's Theses

  1. DESIGN AND SIMULATION OF A DUAL-INPUT HYBRID CONVERTER FOR ENERGY HARVESTING APPLICATIONS, Aminu Abdulkarim, 2024.
  2. Active Loaded Source-Coupled Logic (ALSCL) and Circuit Realizations, Shuai Wang, 2023.
  3. Efficient FPGA Implementation on Convolutional Multiply-Add Operations, Taha Hussain, 2022.

7. Publications

7.1. Papers published in internationally refereed journals (Scopus Indexed)

  1. Cini U., Wang S., Active Loaded Source-Coupled Logic: Applications and Performance Comparison, AEU - International Journal of Electronics and Communications, (2023), 169(), 154750, .
  2. ÇİNİ U., Rail-to-Rail Buffer Amplifier with Adaptive Biasing for Flat Panel Displays, Electrica, (2021), Accepted for publication(), 1-10, .
  3. Cini U., Toker A., DVCC-based very low-offset current-mode instrumentation amplifier, International Journal of Electronics, (2017), (), 1346-1357, .
  4. Cini U., Kocyigit G., Limited Carry-Propagate Multiply-Accumulate Unit Design for Reconfigurable Systems, Elektronika ir Elektrotechnika, (2017), (), 36-39, .
  5. Cini U., Aktan M., Dual-mode OTA based biquadratic filter suitable for current-mode applications, AEU - International Journal of Electronics and Communications, (2017), 80(), 43-47, .

7.3. Assertions presented in international scientific congresses and published in the proceedings

  1. , A New Source-Coupled Logic Technique: ALSCL, 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), (04.12.2023), İstanbul
  2. ÇİNİ U., A Low-Power Biasing Scheme for the Rail-to-Rail Buffer/Amplifier Applications, "A Low-Power Biasing Scheme for the Rail-to-Rail Buffer/Amplifier Applications", IEEE ICECS 2021 28th IEEE International Conference on Electronics Circuits and Systems, Dubai, UAE, 2021, (28.11.2021), Dubai

7.4. International books or chapters

7.5. Papers published in national peer-reviewed journals

7.6. Assertions presented in national scientific congresses and published in the proceedings

7.7. Other publications

Books published by national publishers

Book chapters published by national publishers

8. Projects

  1. ŞEKER S., APAYDIN G., ÇİNİ U., ABUNIMA H., KOPACAK N., KRANDA E., BAP projesi, Elektrik-Elektronik Mühendisliği Bölümünde Güç Sistemleri ve Elektrik Makineleri Laboratuvarı Kurulması, (Researcher), (Expire date :14.08.2024),

9. Administrative Duties

  1. Öğrenci Danışmanlığı / Student Adviser - 100 -150 Öğrenci Danışmanlığı (2024-Continues)
  2. Laboratuvar - Laboratuvar Sorumlusu (2020-Continues)
  3. Bölüm Başkan Yardımcısı / Deputy Head of Department - Elektronik Mühendisliği (İngilizce) Bölüm Başkan Yardımcısı (2021-2024)
  4. Komisyon Üyesi / Member of Commission - Kalite Komisyonu (Enstitü / Fakülte / MYO) (2024-2024)
  5. Komisyon Üyesi / Member of Commission - Staj Komisyonu (Enstitü / Fakülte / MYO) (2022-Continues)
  6. Komisyon Üyesi / Member of Commission - Erasmus ve Dış İlişkiler Komisyonu (2021-Continues)
  7. Komisyon Üyesi / Member of Commission - Uluslararası Öğrenciler Akademik Komisyonu (2019-Continues)

10. Scientific Memberships

11. Awards

12. Coourses recently given

Academic Year Semester Course name Hours Number of Students
Theoretical Application
2023-2024 Spring Digital System Design with FPGAs (Master) - Group 2 3 0 0
Logic Circuits (Undergraduate) - Group 2 3 0 346
Introduction to Digital Systems (Undergraduate) - Group 2 3 0 156
Electronics II (Undergraduate) - Group 2 3 0 102
Advanced Digital Design (Undergraduate) - Group 2 3 0 96
Graduation Thesis (Undergraduate) - Group 2 0 4 22
Fall Computer Tools for Electrical Engineering (Undergraduate) - Group 2 3 0 162
Digital Systems Design (Undergraduate) - Group 2 3 2 172
Electronics I (Undergraduate) - Group 2 3 0 122
Graduation Project (Undergraduate) - Group 2 2 0 20

Created: 22.12.2024